1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to the testing of integrated circuits.
2. Description of the Related Art
Integrated circuit (IC) technology has made rapid advances in recent years. One area where IC technology has noticeably improved is in operational speed. Processor speeds of over 2 GHz are commonplace nowadays, and bus speeds are approaching 1 GHz. While these advances result in considerably greater performance, they also create problems. One such problem involves the testing of these IC's.
While some internal functionality of a high-speed integrated circuit can be tested at full speed (due to clocking by internal phase locked loops), it is often times difficult (if not impossible) to conduct any kind of test of the IC's input/output (I/O) pins at full operational speed. Timing tests are one type of test that is critical for ensuring proper operation of the I/O's of an IC. In such timing tests, it is often times necessary to determine the response time to data input to or output from the various I/O pins on the IC.
Timing tests for an IC may often times be conducted on automated test equipment (ATE). However, using ATE to conduct accurate timing tests is often times problematic, particularly with the higher operational speeds of newer generations of IC's. As bus speeds (and thus the speeds at which I/O's operate) have increased with newer generations of IC's, ATE capabilities have not increased proportionally. Thus, newer ATE often times lacks the accuracy necessary for ensuring proper timing tests. This lack of accuracy may sometimes be compensated for using special tester setups, but these setups may not be conducive to high volume manufacturing.
Regardless of any special setups, the lack of accuracy of ATE relative to the operational speeds may result in tradeoffs between the conducting of timing tests with wide margins (resulting in a higher product yield at the risk of sacrificing quality) or with narrow margins (resulting in a lower yield and the possibility of good product being scrapped). Alternatively, an IC manufacturer could choose to wait until a new generation of ATE is introduced having the requisite accuracy, but this would result in an unacceptable time-to-market for the manufacturer and put them at a significant competitive disadvantage. This is compounded by the fact that ATE represents a large capital investment, and thus adds significantly to the cost of a product. With the operational speed of IC's (including the I/O speed) advancing rapidly, IC manufacturers may be forced to purchase new ATE with each new product generation in order to ensure product quality and functionality, resulting in a more expensive finished product in a competitive market.